The present invention relates to a clock pulse generator and, more particularly, to a clock pulse generator which is incorporated in a CMOS (complementary metal oxide semiconductor) integrated circuit device and which generates clock signals in synchronism with an externally supplied timing signal.
The inventors of the present invention have proposed in Japanese Patent Laid-Open No. Hei 2-230821 a clock pulse generator having compensating means for varying the range of oscillated frequencies of a VCO (voltage-controlled oscillator) constituting part of a PLL circuit, with respect to the frequency of a timing signal fed from an external terminal. Equipped with its compensating means, the proposed clock pulse generator generates clock signals in a stable manner over a wide range of frequencies.